1. Field of the Invention
The invention relates to a display device. Particularly, the invention relates to a controller driver for driving a display panel.
2. Description of Related Art
Referring to FIG. 1, FIG. 1 is a block schematic diagram of a conventional controller driver 120 of a display panel 140. The controller driver 120 includes a system interface circuit 122, a memory control circuit 124, an image data memory 126, a timing control circuit 128, a data line driving circuit 132, a scan line driving circuit 134 and a grayscale voltage generating circuit 136. The system interface circuit 122 is coupled to an external processor 110, and the data line driving circuit 132 and the scan line driving circuit 134 are coupled to the display panel 140.
When the controller driver 120 is operated in a normal operation mode, the processor 110 transmits display data to the memory control circuit 124 through the system interface circuit 122. The memory control circuit 124 temporarily stores the display data in the image data memory 126. The processor 110 transmits a control signal to the timing control circuit 128 through the system interface circuit 122. The timing control circuit 128 sends corresponding control signals to the memory control circuit 124, the data line driving circuit 132 and the scan line driving circuit 134 in timing. For example, the timing control circuit 128 reads image data corresponding to a same scan line in an image frame from the image data memory 126 through the memory control circuit 124, and latches the image data to data output terminals of the memory control circuit 124. After the memory control circuit 124 completes reading the image data, the timing control circuit 128 further controls the data line driving circuit 132 and the scan line driving circuit 134 to transmit the image data latched to the data output terminals of the memory control circuit 124 to pixels of the corresponding scan line in the display panel 140. Deduced by analogy, the controller driver 120 transmits image data corresponding to other scan lines in the image frame to the pixels of the corresponding scan lines in the display panel 140, so as to display a corresponding image.
FIG. 2A is a timing diagram of the controller driver 120 of FIG. 1 in the normal operation mode. Here, it is assumed that the scan line driving circuit 134 includes a plurality of output terminals respectively driving a first scan line G1, a second scan line G2, a third scan line G3, an Nth scan line GN and other scan lines of the display panel 140. A gate address GA varied every a predetermined time is transmitted from the timing control circuit 128. The scan line driving circuit 134 sequentially drives the scan lines of the display panel 140 according to the gate address GA. As shown in an upper part of FIG. 2A, a fixed time, i.e. a frame time is divided into N gate driving periods T. Under control of the timing control circuit 128, the scan line driving circuit 134 sequentially drives one of the scan lines of the display panel 140 at different gate driving periods T.
A lower part of FIG. 2A includes (1) display data of a data line driver in the data line driving circuit 132; (2) latch signals used to control the data output terminals of the memory control circuit 124 that are transmitted from the timing control circuit 128; (3) reading pulses used to control the image data memory 126 through the memory control circuit 124 that are transmitted from the timing control circuit 128.
When the controller driver 120 is operated in a test operation mode, the external processor 110 writes a test pattern into the image data memory 126 through the system interface circuit 122 and the memory control circuit 124 in advance. After the test pattern is written into the image data memory 126, the timing control circuit 128 reads the test pattern from the image data memory 126 through the memory control circuit 124 in timing, and transmits the test pattern to the data line driving circuit 132. The timing control circuit 128 further controls the data line driving circuit 132 to output the test pattern. An external test equipment is used to measure the output of the data line driving circuit 132 to determine whether the controller driver 120 passes the test.
Referring to FIG. 2B, FIG. 2B is a test flow of the controller driver 120 of FIG. 1 in the test operation mode. First, in step S205, the external processor 110 (for example, a test platform) activates the controller driver 120, and the controller driver 120 enters the test operation mode in response to a control signal TE provided from the external processor 110. In step S210, the external process 110 (for example, the test platform) writes the test pattern into the image data memory 126 through a writing path, i.e. through the system interface circuit 122 and the memory control circuit 124. Then, in step S220, the test pattern is read from the image data memory 126 through a reading path, namely, the memory control circuit 124 reads the test pattern from the image data memory 126 to the data line driving circuit 132. The timing control circuit 128 further control the data line driving circuit 132 for outputting the test pattern. Then, in step S230, by measuring the output of the data line driving circuit 132, it is determined whether the controller driver 120 passes the test. If the controller driver 120 does not pass the test, in step S250, the test flow is ended, and if the controller driver 120 passes the test, in step S240, it is determined whether a last test pattern is tested, and if yes, the step S250 is executed to end the test flow. If the current test pattern is not the last test pattern, the step S210 is returned, and the external processor 110 writes a next test pattern to the image data memory 126 to perform a next test procedure, i.e. the steps S210-S250 are repeated.
In the test flow, a display timing diagram of the controller driver 120 is shown in FIG. 3. The display timing diagram includes (1) image data memory read enable signals of the memory control circuit 124; (2) row addresses; (3) outputs of the image data memory 126; (4) latches enable signals of the data output terminals of the memory control circuit 124; (5) data line driving enable signals of the data line driving circuit 132; and (6) data line outputs of the data line driving circuit 132.
When the memory control circuit 124 receives pulses of the row address and the image data memory read enable signal sent by the timing control circuit 128, it completes reading data from the image data memory 126 within a predetermined time. For example, as shown in FIG. 3, after the memory control circuit 124 receives a pulse of the image data memory read enable signal, it reads the image data memory 126 according to the row address within a time section TR, and reads the corresponding display data from the image data memory 126 after the time section TR, for example, Nth row display data of FIG. 3. During the time section TR, the data line driving enable signal outputs to the data line driving circuit 132 by the timing control circuit 128 is in a logic high state, and the data line driving circuit 132 outputs (N−1)th row display data.
After the time section TR, the memory control circuit 124 completes the read operation of the Nth row display data, and now the timing control circuit 128 transmits a latch enable signal to the memory control circuit 124. After the memory control circuit 124 receives the pulse of the latch enable signal, it latches the Nth row display data to the data output terminals of the memory control circuit 124, and provides the Nth row display data to the data line driving circuit 132. Therefore, the data line driving circuit 132 can provide the Nth row display data to the data lines of the display panel 140 when the data line driving enable signal outputted by the timing control circuit 128 is in the logic high state. Deduced by analogy, the memory control circuit 124 sequentially outputs the (N+1)th display data to the (N+n−1)th display data according to the pulses of the image data memory read enable signal.
Regarding the conventional controller driver 120, both of the normal operation mode and the test operation mode, a same transmission channel is used to transmit the display data and the test pattern. Based on the above architecture, when the test operation is performed on the controller driver 120, interface transmission efficiency and a limiting condition of the transmission channel have to be considered, and the probably generated delays may greatly increase a testing time and reduce a testing efficiency.
For example, regarding a controller driver IC used in a mobile phone, the testing time is relatively long, and a waiting time is required during data testing, where the waiting time includes a. a time for writing test data into a static random access memory (SRAM, which is equivalent to the image data memory 126); b. a time for sending the test data from the SRAM to a source driver (which is equivalent to the data line driving circuit 132). The above two operations are all related to a SRAM accessing speed.